Almost done, just have to check the examples

2026-03-11 20:57:23 +01:00 · 2026-03-11 20:57:23 +01:00 · 493f7b9785
commit 493f7b9785
parent 381dc5c93d
5 changed files with 14 additions and 14 deletions
--- a/src/modules/solver/moduleSolver.f90
+++ b/src/modules/solver/moduleSolver.f90
@ -564,7 +564,7 @@ MODULE moduleSolver
        !Reset CPU Time counter
        counterCPUTime = 0

-        CALL printTime(timeStep == 0)
+        CALL writeTime(timeStep == 0)

      END IF